Power Your Project with the Flexibility and Freedom of AAEON SMARC Modules

Smart Mobility ARChitecture (SMARC) is a standard used for designing computer-on-modules. A SMARC module typically includes a CPU or SoC, RAM, boot flash memory, voltage regulators, and essential interfaces. Along the module’s edge are gold-plated contacts, often called “gold fingers,” which connect to an edge connector on the carrier board. This board adds extra functionality such as audio codecs, touch controllers, or wireless components.

The SMARC specification assigns each interface’s signals to specific connector pins, using a fixed layout. This ensures full compatibility between modules from different manufacturers. It also means you can use the same carrier board across multiple SMARC modules, making it easier to scale, accelerate development, and keep your hardware up to date.

Why choose SMARC modules

• Vendor-independent standard, allowing sourcing from multiple suppliers and improving availability
• Processor-agnostic, with support for both ARM and x86 CPUs from various vendors
• Well-balanced selection of interfaces
• Reliable MXM3-style connector
• Versatile and scalable design
• Compact footprint

SMARC module features overview

• Pin layout optimised for both ARM and x86 processor architectures
• Two standard module sizes:
• 82 x 50 mm
• 82 x 80 mm
• Rugged, vibration-resistant carrier board connector
• 314-pin, 0,5 mm pitch connector originally designed for MXM3 graphics cards
• Note: The SMARC module’s pin configuration does not correspond to that of MXM3
• Multiple sources for the carrier connector
• Low-profile construction
• Module height starts at just 1,5 mm (from the top of the carrier to the bottom of the module)
• Other height options include 2,7 mm, 5 mm, and 8 mm
• Total assembly height (from the top of the carrier to the tallest module component) can be less than 6 mm
• Excellent signal integrity, suitable for data rate signals of 2,5; 5; and 8 GHz, supporting PCIe Gen 1, Gen 2, Gen 3, and Gen 4
• Module input voltage range: 4,75 V to 5,25 V or 3,0 V to 5,25 V (module dependent)
• Compatible with 3,6 V lithium-ion batteries
• Single-supply operation with no separate backup voltage required
• Power pins support up to 5 A
• Low-power design
• The standard power envelope below 6 W, with configurations up to 15 W supported
• Fanless operation
• Low standby power consumption
• Battery-ready design
• I/O voltage: 1,8 V

Required and optional features

According to the SMARC specification, every module shall provide:

• I2C for power management
• General-purpose I2C
• UART (Rx, Tx, RTS, CTS)
• UART (Rx, Tx)
• USB 2.0 Host
• 12 GPIO with interrupt capability
• Camera GPIO (only if a camera is supported)
• Boot selection interface

Additional interfaces or functions are indicated using the following keywords:

• Should – recommended but not mandatory
• May – optional and less commonly used
• Alternate – optional interface implemented on pins that are also designated for other functions

AAEON SMARC modules

AAEON offers x86-64-based modules uCOM-ASL and uCOM-ADN, as well as ARM-based modules uCOM-M700, uCOM-IMX93, and uCOM-IMX8P.

You can easily compare module features on our website in the computers on module section. AAEON is also working on new modules based on the Rockchip RK3558 and Qualcomm QCS6490, expected to launch in Q3 2025. Follow our blog to stay up to date with the latest product news.

All current AAEON SMARC modules follow the SMARC 2.1.1 specification. The latest version, SMARC 2.2, retains full compatibility with 2.1.1 and introduces the following updates:

• Adds Soundwire as an alternative to I2S2 on pins S50, S51, S52 and S53
• Extends PCIe support up to Gen 4
• Updates feature classifications for USB0, USB1, and USB2 (bracketed notes apply to SMARC 2.1):
• USB0: USB2.0 shall (may, USB0 shall be implemented as Host or OTG/Client )
• USB1: USB2.0 should (shall)
• USB2: USB 3.2 Gen1x1: should (may)  
• If SPI is implemented, the following chip select signals apply:
• SPI0_CS0#: shall, SPI0_CS1#: should
• SPI1_CS0#: shall, SPI1_CS1#: should
• Specifies latency of GPIO interrupts. Inputs with the lowest latency interrupts should be mapped to GPIO6-13, where GPIO6 has the lowest latency. GPIO0-5 may have the highest latency.

AAEON SMARC modules are shipped without a pre-installed operating system. Preconfigured OS images for the ECB-960T-A15 carrier board are available on request:

• uCOM-IMX8P, Debian 12, Kernel 5.15
• uCOM-IMX93, uCOM-M700 – available on request

Source code for Yocto Linux BSPs is available on AAEON’s GitHub (registration required):

• uCOM-IMX93 – Yocto 5.0 (Kernel 6.6.23) with GUI
• uCOM-IMX8P and uCOM-M700 Yocto 4.0 (Kernel 5.15)

For x86-64 modules, Windows or Linux can be installed just like on a standard PC. Supported OS options include Ubuntu 22.04.2, Windows 10 (64-bit), and Windows 11. A carrier board is required, and we recommend starting with the ECB-960T-A15.

Design support

AAEON offers a free review of your carrier board schematic within five working days of request submission. That is not all. You can also explore the AAEON Q-Service for additional resources.

AAEON currently offers two reference carrier boards: ECB-960T-A15-0001 for x86-64 SMARC modules and ECB-960T-A15-0002 for ARM-based modules. PDF schematics will be available soon through the AAEON Q-Service.

AAEON also provides 3D models for all modules. These are particularly useful if you need to design a custom heat spreader or heatsink.

AAEON SMARC modules are now available in our computers on module section, with selected models in stock. Looking for something else? We can also source additional products on request. Full technical specs are available on our website.