DataRAID is a firmware algorithm that ensures data integrity by creating parity to verify the completeness and correctness of the existing data in the flash memory, developed specifically for the 3D NAND flash. If the firmware is unable to repair the data using the ECC (Error-correcting code), the RAID algorithm will use parity and repair corrupted data.
End-to-end Data Protection
It is a feature that extends error control to cover the entire path from the computer to the flash memory chips and back.
● As data passes from the computer to the SSD cache, firmware calculates CRC parity from it and append it to the data. ● When the data with CRC parity are moved from the cache to the sector buffer, the CRC parity is checked. ● The firmware then calculates the BCH (LDPC) ECC codes for data and writes them together with the data and their CRC parity to the flash memory.
When data is read from the NAND, the process occurs in reverse order: ● The firmware reads data with attached BCH (LDPC) error correction codes, checks data and repairs errors if necessary, ● The firmware then moves data to SSD cache, calculates CRC parity and compare it with parity stored with data.
Smart Read Refresh
In order to read status from one cell on a bit line, all other cells on the same bit line must be turned on so that the current proportional to the charge stored in the cell can flow through the sensing amplifier. This can be achieved by applying a pass-through voltage to the word lines of unread cells.
During the reading, the substrate is attached to the GND just like writing. The pass-through voltage on word lines is not as high as the programming voltage but still produces a “weak programming” effect that can shift the threshold voltage of the cells to which the pass-through voltage is connected.
Smart Read Refresh
During each reach command, the controller will perform a two-stage check on the target block. First, it checks if the block has been marked as “need to refresh.” If it has, the block will be refreshed before being read, which means that all programmed pages from this block are copied to free pages in other blocks and then block is erased. If it has not, the controller will check the number of error bits currently present. If the number of errors meets or exceeds the threshold, it will mark the block “need to refresh,” meaning it will be refreshed during the next read operation. The threshold is of course set to a value at which the ECC algorithm is still able to correct errors.
After choosing a specific SSD, customers often have difficulty understanding the actual behaviour in the field, beyond the basic data such as SSD status and remaining capacity. Therefore, they cannot take full advantage of SSD.
The first step is to determine the ideal SSD for a specific application, including choosing the most suitable firmware. This can be achieved with Apacer's CoreAnalyzer2 software. It works at the firmware level and monitors temperature, SATA commands, random or sequential read/write behaviour, whether the partition is aligned with physical 4KB sectors and whether the data is read/written always as multiples of 4KB ((4K alignment), number of programming/erasing cycles, power failure count, idle time, and how often the drive is accessed.
The customer can use Coreanalyzer2 during workload simulation or during field tests if the simulation is not possible. After testing, the customer can download the log file and send it to Apacer for analysis. Apacer analyzes it to assess whether the SSD is suitable for this particular application or recommends one or more SSDs that are most appropriate, along with possible firmware modifications that might be useful.
Although this technology is not brand new, it is worth to note that all new Apacer SSDs use page mapping instead of hybrid block mapping.
In page mapping, the mapping table entry consists of LPN (logical page number) and PPN (physical page number). When a request to write to a logical page comes, the mapping table searches for that physical page. If it already contains data, the page is invalidated and the required data is written to the available free page. After writing, the mapping table in RAM and NAND flash is updated.
Page mapping has the advantage of writing data to any free page in Flash memory, which increases the flexibility of storage management. Random write doesn‘t require multiple page copies and block erase. Page mapping performs better when enough free pages are available. Invalidated pages, "garbage" must, therefore, be reclaimed to free up space for new data. The firmware, therefore, uses an efficient "garbage collection" technique.
Page mapping requires a large amount of both RAM and flash memory for the mapping table. This has been a problem in the past, especially for price-sensitive embedded systems. Currently, the cost of RAM and flash has fallen to such an extent that page mapping is used even for some microSD memory cards.
To reduce write amplification and increase endurance and performance, some of Apacer’s SSDs support over-provisioning. With this technology, 7% or more of disk space is reserved for the firmware to perform “garbage collection”, wear-leveling and replacement of new bad blocks. Reserved space is not accessible to users, only to the firmware.
TCG Opal 2.0
Developed by the Trusted Computing Group (TCG), the Opal Storage Specification is a set of security specifications used for applying hardware-based encryption to storage devices. In other words, it is a specification for self-encrypting drives (SED) so that all data on the drive is always encrypted, without the use of third-party encryption solutions.
The Trusted Computing Group Storage Workgroup created the Opal Security Subsystem Class (SSC), also called “Opal SSC” or “Opal” for short, as a security management protocol for storage devices. The class defines specifications concerning file management on storage devices, and defines class level permissions for storage/retrieval of files, thus protecting user data. Devices conforming to Opal SSC specifications are sometimes referred to as TCG Opal devices.
AES 256-bit encryption is a popular way of securing drives since it’s extremely resilient to brute-force attacks. Encryption is done in SSD itself by using special HW designed for this task which can be faster than software solutions.
AES 256, Instant Keychange
SSDs that support HW encryption also offer another way to safe erase – instant keychange. When the Instant Keychange command is issued, a new key is generated that replaces the original key in Flash in less than a second. Because the new key does not match the old one when the computer attempts to access the data, they will be unavailable due to AES key authentication failure. The data has not been erased in the conventional sense (rewritten to 0 or 1), but they are unreadable and therefore protected.
In the beginning, the SSD allows writing at full speed. When the temperature reaches the threshold A, the disk begins to limit the write speed, allowing it to cool down gradually. As soon as the temperature B (B<A) is reached, the SSD gradually enables faster writing.
To obtain maximum performance, it is necessary to avoid thermal throttling by good heat transfer from SSD to chassis or heatsink. This is especially true for M.2 SSDs because they have a small area that can dissipate heat.
Find more information about these technologies right here.
Technology Available for Particular Series
You can find a summary of the technologies available for the particular SSD series in the attachedtable.
SSD Availability Overview
The attached brochure gives you an overview of Apacer SSDs, memory cards and USB sticks. It contains almost the entire offer. For products not listed in this brochure, please visit the Apacer and SOS Electronic websites.
Take the opportunity to order samples for testing for discount prices. For information about available products, please visit our website.